1. Field of the Invention
The present invention relates to a delay circuit that is applied to, for example, semiconductor devices such as semiconductor memories, and has a function of a filter for removing noise.
2. Description of the Related Art
A plurality of delay circuits having various delay times are used in semiconductor devices. The most typical delay circuit in semiconductor devices is an inverter chain including a plurality of inverter circuits. Supposing that one inverter circuit has a delay time of 1 nsec, an inverter chain including ten inverter circuits can have a delay time of 10 nsec. However, characteristics of the inverter circuit vary according to the power supply voltage, temperature, and processing precision of the transistors included in the inverter circuit. Therefore, the delay time of a delay circuit of the inverter chain type often varies greatly. There is also a delay circuit of a type using an RC time constant obtained by combining a resistor element with a capacitor. In this delay circuit as well, however, the delay time varies according to the processing precision of the resistor element and the capacitor and the temperature.
In recent years, improved delay circuits have been proposed so as to provide a stable delay time by compensating for the processing dispersion of the transistors included in the delay circuit, the change of the power supply voltage, and the temperature change. Such delay circuits are disclosed in Japanese Patent Application KOKAI Publication No. 8-70242, U.S. Pat. No. 5,627,488, and U.S. Pat. No. 5,969,557. In addition, a delay circuit having a delay time that becomes shorter as the power supply voltage rises is disclosed in Japanese Patent Application KOKAI Publication No. 8-190798.
As the power supply voltage in the semiconductor devices becomes lower, it is becoming impossible to achieve a stable delay time in a conventional delay circuit. In other words, delays of a logic circuit, such as an inverter circuit that forms the delay circuit, and an output circuit itself that forms a delay signal are actualized. Even if the delay circuit itself is stable, therefore, the resultant delay time varies greatly according to the power supply voltage. Therefore, it is desired that a delay circuit capable of providing a stable delay time irrespective of the power supply voltage is developed.